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Sasken Communications Technical Interview Questions

Posted on :23-03-2016
Q1. How Jk F/F can be converted into T F/F.


Q2. Difference between display and write in Verilog.?


Q3. ASIC flow steps? (RTL design ->Functional Verification->Synthesis ->STA->Place and route)


Q4. Difference between Latch and F/F?Which is faster?


Q5. Difference/Comparison between DRAM and SRAM?


Q6. What happens to Vth if temp Increases>?


Q7. In a negative feedback control System ,If feed factor Increases what happens to Gain and Bandwidth?


Q8. NMOS and PMOS will pass which value without degradation?[NMOS -0 and PMOS -1]


Q9. AB+BC 


(i) Cant be further reducible and glitch

(ii) Can reducible further and cant glitch


Q10. Which is faster :read cache or write cache?


Q11. Noise Margin Definition?


Q12. What happens to power If Vth increases In CMOS?


Q13. enum = {a=1,b=5,c,d} What is the c and d?


Q14. (A+B) is equivalent to?

Q15. How can we Increase the slope of Transfer charcteristics of a CMOS?


(i)Increasing W/L ratio of PMOS and NMOS In the same proportion

(ii) Increasing W/L ratio of PMOS and NMOS In different proportion

(iii) Increasing W/L ratio of PMOS only

(iv) Increasing W/L ratio of NMOS only



Descriptive Questions

Q1. What happens If we interchange PMOS and NMOS in a CMOS Inverter?


Q2. Why PMOS width should be greater than NMOS?


Q3

int a =0;

If(a++) print (Example1);

else if (++a) print (example2);


(i)What is the output if the program?

(ii)What is the value of i?


Q4. What are the advantages and disadvantages of Pipeline operation?


Q5. Draw the output waveform?

(i) initial begin

Y = #5 0;

Y = #3 1;

Y = # 8 0;

(ii) Y


  
   






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