BE/B.Tech, ME/M.Tech Fresher’s required for the position Intern-Technical in Synopsys at Delhi. Interested and eligible candidates who have strong skill sets on desired profile can apply online for the requirement with the link given below. Find the job description, eligibility criteria, exact venue and interview details for more information. Synopsys Hiring BE/B.Tech, ME/M.Tech freshers 2015 for Intern-Technical at Bangalore. Candidates who have completed BE/B.Tech, ME/M.Tech can apply for this job from Synopsys.
Company Name: Synopsys
Qualification: BE/B.Tech, ME/M.Tech
Job Post Name: Intern-Technical
Job Location: Delhi
Total No of Vacancy: NA
Would be part of the team developing Verification IPs and / or working on SoC verification. Person would be working on different phases of development, including design, coding, test planning, test execution, coverage etc.
The responsibility would also include enhancement of the existing Verification IP products, analyzing customer’s target environment, usage, problems and help them with debugging and providing solutions.
Candidates should possess minimum bachelor’s degree in EE.
Good Knowlwdge of System Verilog
Methodology knowledge- exposure of any verification methodology (OVM,UVM,VMM)
Protocol Knowledge – theoretical knowledge of any one of the protocols (AMBA AHB & AXI / USB / PCIe/Ethernet/SATA/OCP/MIPI/HDMI/I2C/SIO
1. Aptitude Test
2. Technical and HR Interview
Document Required (Original and Photocopies):
1. SSC Marksheet
2. HSC/Diploma Marksheet
3. Graduation & Post Graduation all years’ mark sheets
4. Photo ID proof (Pan Card/ Passport / Driving License / College ID)
5. 2 photographs
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results.
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25-01-2017 , 26-01-2017