The candidate should possess Masters or Bachelors in VLSI/Electrical or Electronics background. (0-2+ Years of experience).
Good knowledge of Physical Design (RTL to GDS). (Synthesis, Place and Route, Timing, Physical verification).
Should have good exposure to industry standard EDA tools (Synopsys/ATOP).
Good skills in Automation (TCL or Perl) a must.
Should have the ability to adapt and work together as a team.
Must possess good problem solving and Analytical thinking.
LOCATION : India
EXPERIENCE : 0-2 Years
JOB DESCRIPTION / DESIRED CANDIDATE PROFILE
The Physical Design Engineer Role as an intergral member of team working for ASIC/FPGA complex processor design.
Role is responsible for RTL to GDS implementation of the GHZ processor subsystem, drive and involvement into chip level aspects, partitioning, floor planning, PNR, physical verification, Timing closure, STA(SSTA), methodology drive and automation.
Xilinx is the world’s leading provider of All Programmable technologies and devices, beyond hardware to software, digital to analog, and single to multiple die in 3D ICs. Only Xilinx has the portfolio to enable design teams to develop All Programmable electronic systems. This expands their system value advantages, addresses the industry’s “programmable imperative” by reducing exploding design costs, and dramatically increases flexibility and lowers risk in a rapidly changing market environment.
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